1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a data transmission circuit.
2. Related Art
A semiconductor memory apparatus stores input data and outputs stored data stored.
FIG. 1 is a diagram illustrating a general semiconductor memory apparatus that includes a data storage area 10, a data transmission circuit 20, and a data input/output circuit 30.
The data storage area 10 stores data received through first and second data lines S_Line and S_LineB, and outputs the stored data through the first and second data lines S_Line and S_LineB.
The data transmission circuit 20 transmits the data, which is received through the first and second data lines S_Line and S_LineB, to third and fourth data lines L_Line and L_LineB in a read operation. The data transmission circuit 20 transmits data, which is received through the third and fourth data lines L_Line and L_LineB, to the first and second data lines S_Line and S_LineB in a write operation.
The data input/output circuit 30 transmits data Data_in received from an exterior device to the third and fourth data lines L_Line and L_LineB, and outputs data Data_out received through the third and fourth data lines L_Line and L_LineB to an exterior device.
The data output from the data storage area 10, that is, the voltage difference between the first and second data lines S_Line and S_LineB, is detected and amplified by the data transmission circuit 20 and is output through the third and fourth data lines L_Line and L_LineB. The data input/output circuit 30 then transmits the data on the third and fourth data lines L_Line and L_LineB to an exterior device on the Data_out line. The data input/output circuit 30 may also receive data from an exterior device via the Data_in line, and transmits the data on the third and fourth data lines L_Line and L_LineB to the data transmission circuit 20. The data transmission circuit 20 transmits the data received on the third and fourth data lines L_Line and L_LineB to the data storage area 10 via the first and second data lines S_Line and S_LineB.
In general, the data transmission circuit 20 is arranged adjacent to the data storage area 10 as compared with the data input/output circuit 30. Therefore, the lengths of the first and second data lines S_Line and S_LineB may be shorter than the lengths of the third and fourth data lines L_Line and L_LineB. In other words, the loading of the first and second data lines S_Line and S_LineB is smaller than the loading of the third and fourth data lines L_Line and L_LineB.
The data transmission circuit 20 transmits data to the first and second data lines S_Line and S_LineB in the write operation, and to the third and fourth data lines L_Line and L_LineB in the read operation. The data transmission circuit 20 detects and amplifies the voltage level difference between the first and second data lines S_Line and S_LineB, and transmits the amplified voltage difference to the third and fourth data lines L_Line and L_LineB in the read operation.
The data transmission circuit 20 detects and amplifies the voltage difference between the first and second data lines S_Line and S_LineB during the read operation. Therefore, the data transmission circuit 20 performs the detection and amplification operation in the read operation even when the voltage level difference between the third and fourth data lines L_Line and L_LineB is substantially equal to or more than a desired level.